1. Field of the Invention
This invention relates to a metal-insulator-semiconductor (MIS) type field effect transistor (FET). More particularly, it relates to a minute size MIS type FET having a short channel between a source and a drain.
2. Description of the Background Art
Referring to a diagrammatic sectional view of FIG. 4, a punch-through phenomenon in a FET is explained. In this figure, on raising a voltage applied across a drain 10b and a source 10a of a second conductivity type formed on a semiconductor substrate 1 of a first conductivity type, widths of depletion layers 15a and 15b are increased. The widths of the layers 15a and 15b are increased particularly in a deeper region where the effect of the voltage of the gate electrode 8 becomes extinct. If the depletion layer 15b on the drain side and the depletion layer 15a on the source side connect to each other at a region deeper than a channel layer 9, the carriers flow from the source 10a to the drain 10b through the depletion layers, as shown by an arrow. Thus the punch-through phenomenon means the flow of carriers which can not be controlled by the gate electrode 8 and which proceeds from the source 10a towards the drain 10b through a region deeper than the channel layer 9.
The source 10a and the drain 10b usually have a high impurity concentration of approximately 10.sup.20 cm.sup.-3, whereas the substrate 1 has a low impurity concentration of approximately 10.sup.15 cm.sup.-3. Thus the depletion layer spreads wider on the substrate side in the vicinity of each boundary of the source 10a and the drain 10b.
As may be seen from FIG. 4, the punch-through phenomenon is most likely to occur when the channel 9 is of shorter length and the source 10a and the drain 10b are closer to each other. That is, a small size FET with a short channel length is more susceptible to the punch-through phenomenon. A demand exists, however for a smaller and smaller size FET for raising the degree of integration of semiconductor IC devices. Thus the small size FET having a channel length less than 2 .mu.m is formed within a well formed in a substrate and having an impurity concentration higher than that of the substrate. The high impurity concentration in the well acts to reduce the widths of the depletion layers in the vicinity of the boundaries of the source and the drain to suppress the punch-through phenomenon.
Referring to FIGS. 5A to 5G, an example of the conventional method for producing the small-size FET is explained.
First referring to FIG. 5A, an oxide film 2 is formed by thermal oxidation on a major surface of a silicon substrate 1. A nitride film 3 is formed by a chemical vapor deposition (CVD) method on the oxide film 2. A first conductivity type impurity layer 11 for forming the well is formed by implanting impurity ions through both the nitride film 3 and the oxide film 2.
Referring to FIG. 5B, impurities in the impurity layer 11 are driven to a depth of 4 to 5 .mu.m by diffusion by a heat treatment at a high temperature of 1180.degree. C. for six hours or more, to form a well 11a having an impurity concentration higher than that of the substrate 1.
Referring to FIG. 5C, the nitride film 3 is patterned using a resist mask 4 to form a nitride pattern 3a to expose partial areas of the oxide layer 2. Impurity ions are implanted through the exposed partial area of the oxide film 2 to form a high concentration impurity region 12 of the first conductivity type.
Referring to FIG. 5D, after removal of the resist mask 4, a field oxide film 2a is formed by thermal oxidation using the nitride film pattern 3a as a mask. The nitride film pattern 3a is then removed simultaneously with the oxide film 2 thereunder. The high concentration impurity region 12a remaining below the field oxide film 2a acts to cut a parasitic channel below the field oxide film 2a.
Referring to FIG. 5E, a channel dope layer 7 of the first conductivity type is formed in the vicinity of the surface of the well 11a by ion implantation at a lower energy. The function of the channel dope layer 7 is to control the threshold voltage of the FET. A gate oxide film 13 is then formed on the surface of the well 11a.
Referring to FIG. 5F, an electrically conductive layer is deposited on the gate oxide film 13 by a CVD or vacuum evaporation method and the conductivity layer is then patterned to form a gate electrode 8.
Referring to FIG. 5G, impurities are introduced by ion implantation using the gate electrode and the field oxide film 2a as a mask to form source and drain regions 10 of a second conductivity type. In this manner, a minute size MISFET is formed within the well 11a.
The impurity concentration distribution in the silicon substrate 1 in the cross-section taken along a line 6A-6A in FIG. 5G is shown in FIG. 6A, wherein the abscissa denotes the depth (.mu.m) from the surface of the substrate 1 and the ordinate the impurity concentration (cm.sup.-3). The concentration peak shown by an arrow 7 near the surface of the substrate 1 represents the impurity concentration in the channel dope layer 7. The region indicated by an arrow 11a represents the impurity concentration distribution in the well 11a. The region indicated by an arrow 1 represents the impurity concentration in the substrate 1 itself.
FIG. 6B is similar to FIG. 6A but shows the impurity concentration in the sectional plane taken along a line 6B-6B in FIG. 5G. A straight vertical line shown by an arrow 2a indicates the bottom surface of the field oxide film 2a. The concentration peak beneath the bottom of the field oxide film 2a, indicated by an arrow 12a, represents an impurity concentration distribution in a channel cut region 12a.
Referring to FIG. 7, there is shown the effect of the impurity concentration on the carrier mobility in the silicon. The abscissa represents the total impurity concentration (cm.sup.-3) and the ordinate the mobility cm.sup.-2 /v.sec). A curve 7A shows the electron mobility and a curve 7B the hole mobility. As described hereinabove, a well having a high impurity concentration is desirable to prevent the punch-through phenomenon effectively in the small size FET. However, as may be seen from FIG. 6A, if the impurity concentration in the well 11a is increased, the impurity concentration in the channel layer 9 is also increased inevitably. In this case, as may be seen from FIG. 7, the carrier mobility in the channel 9 is lowered, and then the operating speed of the FET is lowered. Particularly, when the total impurity concentration becomes higher than 10.sup.16 cm.sup.-3, the carrier mobility is lowered abruptly.
As described hereinabove, the conventional method for preparing the FET suffers from an inconvenience that the impurity concentration in the well must be increased to reduce the size of the FET and, on the other hand, if the impurity concentration in the well is increased, the operating speed of the FET is lowered.